In an effort to reduce the power consumption of a semiconductor device such as, for example, a processor operating in synchronization with a clock signal, there has been proposed a Dynamic Voltage and Frequency Scaling (DVFS) method of changing a voltage and a frequency dynamically. Such a kind of semiconductor device employs a clock gating method that stops supplying of a clock to an inactive circuit block so as to further reduce the power consumption.
In the clock gating method, a clock gating circuit for interrupting the supply of the clock to the circuit block according to a logic of an enable signal is inserted into an input path of the clock to the circuit block. In the clock gating circuit, the timing of a transition edge of the enable signal for a transition edge of the clock varies along with a change in frequency of the clock. For this reason, a timing constraint of the enable signal may not be satisfied due to, for example, an occurrence of a glitch in a clock output from the clock gating circuit depending on the clock frequency.
When it is determined by timing verification of the circuit block that the timing constraint of the enable signal is not satisfied, the clock gating circuit is not inserted into the circuit block or the clock gating circuit is changed to a circuit satisfying the timing constraint. In addition, the glitch occurring in the clock is suppressed by arranging clock gating circuits in series on a clock tree.
In a semiconductor device which dynamically changes a clock frequency, whether to insert a clock gating circuit based on a timing constraint of an enable signal is determined by the maximum frequency at which the semiconductor device may be operated. For this reason, the clock gating circuit is not inserted into a circuit block satisfying the timing constraint of the enable signal at a clock frequency lower than the maximum clock frequency, and the clock is always supplied to the circuit block. Accordingly, when the semiconductor device is operated at the clock frequency lower than the maximum clock frequency, the circuit block into which the clock gating circuit is not inserted exhibits a less effect in the reduction of power consumption as compared to a circuit block into which the clock gating circuit is inserted.
The followings are reference documents.    [Document 1] Japanese Laid-Open Patent Publication No. 2010-118746,    [Document 2] Japanese Laid-Open Patent Publication No. 2011-164988,    [Document 3] Japanese Laid-Open Patent Publication No. 2002-190528, and    [Document 4] Japanese Laid-Open Patent Publication No. 2010-004352.